There are instances in integrated circuit design wherein voltage level translators are needed to interface circuits requiring different voltage levels. For example, to minimize signal transmission time through data paths, many integrated circuit devices rely on emitter coupled logic (ECL) type voltage swings which are typically on the order of 800 millivolts. One application in which ECL type voltage signals are used in the data path is in static random access memory (SRAM) systems. Such systems include transistor-transistor-logic (TTL) SRAM devices functioning as input/output devices. Accordingly, at various points in the SRAM system, the ECL voltage levels must be converted to CMOS compatible voltages which typically swing between 3.3 volts and ground. However, a delay penalty is incurred in converting the ECL voltage levels to CMOS compatible voltage swings, rail-to-rail, to drive the TTL output. The reduction in time required to translate an input signal is an important objective of any voltage level translator.
In addition to the data paths of systems employing TTL I/O SRAM devices, ECL BiCMOS (Bipolar and CMOS) integrated circuits are faced with the same level conversion problem at the ECL receivers. Most BiCMOS SRAM devices use differential signaling in the data path. The data signal is referenced to the positive supply with a typical logic high level of Vcc-Vbe, where Vbe is the forward voltage drop of a bipolar transistor. The logic low level is typically Vc-Vbe-800 millivolts for a fully static design. Usually a current mirror arrangement is used to convert the small-signal differential input to a full rail single ended output.
One prior art implementation of small signal level translation in an SRAM memory system is disclosed in U.S. Pat. No. 5,384,737 which was issued on Jan. 24, 1995 to Lawrence F. Childs et al. FIG. 1, which is labeled "Prior Art", is a reproduction of an ECL to CMOS level translator that is contained in a collapse detector circuit that is illustrated in FIG. 11 of the referenced patent and which processes differential delayed clock signals. The ECL to CMOS level translator employs a current mirror arrangement in converting the small-signal differential input to a full rail single ended output. However, the field-effect transistor that functions as the constant current source acts as a static load, and the ECL input has a modest slew rate. Consequently, during transitioning, much of the current supplied to the output node is lost and considerable delay is introduced.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a voltage level translator for providing ECL to CMOS signal level translation in circuits for reducing time required to translate an input signal and for minimizing the power requirements to complete signal level translations.